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๊ทธ๊ฒƒ์„ ์•Œ์•„๋ณด์ž - ARM Cortex-M4

ARM Cortex-M4


Cortex-M4


Cortex-M4 ํ”„๋กœ์„ธ์„œ๋Š” M3์— DSP์™€ FPU๋ฅผ ์ถ”๊ฐ€ํ•˜๋ฉด์„œ ์‹œ์žฅ์˜ ํŒ๋„๋ฅผ ๋’คํ”๋“œ๋Š” ์ œํ’ˆ์ด ๋˜์—ˆ์Šต๋‹ˆ๋‹ค.

๊ณ ์„ฑ๋Šฅ ๊ณ ๊ฐ€์˜ DSP๊นŒ์ง€ ํ•„์š”์—†๋Š” ๋ชจํ˜ธํ•œ ๋ถ„์•ผ์— ์ ์žฌ์ ์†Œ๋กœ ์ ์šฉํ•  ์ˆ˜ ์žˆ๋Š” ์ œํ’ˆ์ด ๋˜์–ด ์ฃผ์—ˆ์ง€์š”.


Specifications


Architecture : ARMv7E-M

Bus Interface : 3x AMBA AHB-Lite interface (Harvard bus architecture)

AMBA ATB interface for CoreSight debug components

ISA Support : Thumb/Thumb-2 subset

Pipeline : 3-stages + branch speculation

DSP Extension :

- Single cycle 16/32-bit MAC

- Single cycle dual 16-bit MAC

- 8/16-bit SIMD arithmetic

- Hardware Divide (2~12 Cycles)

Floating-Point Unit : Optional single precision floating point unit IEEE 754 compliant

Memory Protection : Optional 8 region MPU with sub regions and background region

Bit Manipulation : Integrated Bit-field Processing Instructions and Bus Level Bit Banding

Interrupts : Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts

Interrupt Priority Levels : 8 to 256 priority levels

Wakeup Interrupt Controller : Optional

Sleep Modes :

- Integrated WFI and WFE Instructions and Sleep On Exit capability

- Sleep and Deep Sleep Signals

- Optional Retention Mode with Arm Power Management Kit

Debug : Optional JTAG and Serial Wire Debug ports, Up to 8 Breakpoints and 4 Watchpoints

Trace : Optional Instruction (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)


DMIPS/MHz range : 1.25 ~ 1.95

CoreMarkยฎ/MHz : 3.42

MPU(Memory Protection Unit) : Yes (option)

Maximum MPU Regions : 8

Trace (ETM or MTB) : ETMv3 (option)

DSP(Digital Signal Processing) : Yes

Floating Point Hardware : Yes (option SP)

Systick Timer : Yes

Built-in Caches : No

Tightly Coupled Memory : No

Bus Protocol : AHB Lite, APB

Single Cycle Multiply : Yes

CMSIS Support : Yes

Dual Core Lock-Step Support : No


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