ARM Cortex-M3
Cortex-M3 ํ๋ก์ธ์๋ ๋ง์ดํฌ๋ก ์ปจํธ๋กค๋ฌ, ์๋์ฐจ ์์คํ , ์ฐ์ ์ ์ด ์์คํ ๋ฐ ๋ฌด์ ๋คํธ์ํน ๋ฑ
๋ค์ํ ๋ฒ์์ ๋ถ์ผ์์ ์ฌ์ฉํ ์ ์๋ ๊ณ ์ฑ๋ฅ, ์ ๊ฐ์ ํ๋ซํผ์ ์ํด ๊ฐ๋ฐ๋ ํ๋ก์ธ์์ ๋๋ค.
Specifications
Architecture : ARMv7-M
Bus Interface : 3x AMBA AHB-Lite interface (Harvard bus architecture)
AMBA ATB interface for CoreSight debug components
ISA Support : Thumb/Thumb-2 subset
Pipeline : 3-stages
Memory Protection : Optional 8 region MPU with sub regions and background region
Bit Manipulation : Integrated Bit-field Processing Instructions and Bus Level Bit Banding
Interrupts : Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels : 8 to 256 priority levels
Wakeup Interrupt Controller : Optional
Enhanced Instructions : Hardware Divide (2~2 Cycles), single-cycle (32x32) multiply,
Saturated Adjustments Support
Sleep Modes :
- Integrated WFI and WFE Instructions and Sleep On Exit capability
- Sleep and Deep Sleep Signals
- Optional Retention Mode with Arm Power Management Kit
Debug : Optional JTAG and Serial Wire Debug ports, Up to 8 Breakpoints and 4 Watchpoints
Trace : Optional Instruction (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)
DMIPS/MHz range : 1.25 ~ 1.89
CoreMarkยฎ/MHz : 3.34
MPU(Memory Protection Unit) : Yes (option)
Maximum MPU Regions : 8
Trace (ETM or MTB) : ETMv3 (option)
DSP(Digital Signal Processing) : No
Floating Point Hardware : No
Systick Timer : Yes
Built-in Caches : No
Tightly Coupled Memory : No
Bus Protocol : AHB Lite, APB
Single Cycle Multiply : Yes (option)
CMSIS Support : Yes
Dual Core Lock-Step Support : No
'ํ๋์จ์ด > ๊ณต๋ถํ๊ธฐ' ์นดํ ๊ณ ๋ฆฌ์ ๋ค๋ฅธ ๊ธ
๊ทธ๊ฒ์ ์์๋ณด์ - ARM Cortex-M7 (0) | 2020.01.31 |
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