그것을 알아보자 - ARM Cortex-M0+

ARM Cortex-M0+

Cortex-M0+ 프로세서는 Cortex-M0를 기반으로 전체 명령 세트와 도구 호환성을 유지하면서

에너지 소비를 줄이고 성능을 향상시킨 모델이 되겠습니다.

Specifications

Architecture : ARMv6-M

Bus Interface : AMBA AHB-Lite, Von Neumann bus architecture with optional single-cycle I/O I/F

ISA Support : Thumb/Thumb-2 subset

Pipeline : 2-stages

Memory Protection : Optional 8 region MPU with sub regions and background region

Bit Manipulation : Bit banding region can be implemented with Corstone Foundation IP

Interrupts : Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts

Wakeup Interrupt Controller : Optional

Enhanced Instructions : Hardware single-cycle (32x32) multiply option

Sleep Modes :

- Integrated WFI and WFE Instructions and Sleep On Exit capability

- Sleep and Deep Sleep Signals

- Optional Retention Mode with Arm Power Management Kit

Debug : Optional JTAG and Serial Wire Debug ports, Up to 4 Breakpoints and 2 Watchpoints

Trace : Optional Micro Trace Buffer

DMIPS/MHz range : 0.95 ~ 1.36

CoreMark®/MHz : 2.46

MPU(Memory Protection Unit) : Yes (option)

Maximum MPU Regions : 8

Trace (ETM or MTB) : MTB (option)

DSP(Digital Signal Processing) : No

Floating Point Hardware : No

Systick Timer : Yes (option)

Built-in Caches : No

Tightly Coupled Memory : No

Bus Protocol : AHB Lite, Fast I/O

Single Cycle Multiply : Yes (option)

CMSIS Support : Yes

Dual Core Lock-Step Support : No