ARM Cortex-M1
Cortex-M1 ํ๋ก์ธ์๋ ๊ธฐ์กด M0๊ณผ M0+์๋ ๋ฌ๋ฆฌ FPGA์ ์ ํฉํ๊ฒ ์ค๊ณ๋ ์ต์ด์ MCU์ด๋ค.
๋ํ ARM์ด Actel์ด๋ผ๋ ๊ธฐ์ ๊ณผ ํฉ์์ผ๋ก ๊ณต๋ ๊ฐ๋ฐํ ํ๋ก์ธ์๋ก ๋ผ์ด์ผ์ค๋ฅผ ์ทจ๋ํ๊ณ ์๋๋ฐ,
์ด ๊ธฐ์ ์ ๋ง์ดํฌ๋ก์นฉ์ ์ฐํ์ ์๋ ๊ธฐ์ ์ด๋ค.
Specifications
Architecture : ARMv6-M
Bus Interface : AMBA AHB-Lite, Von Neumann bus architecture
with optional Tightly Coupled Memory interface (I-TCM and D-TCM)
ISA Support : Thumb/Thumb-2 subset
Pipeline : 3-stages
SysTick Timer : Optional
Multiplier : Options of fast or area optimized 32x32 multiplier
Bit Manipulation : Bit banding region can be implemented with Corstone Foundation IP
Interrupts : Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts (configurable)
Wakeup Interrupt Controller : None
Interrupt Priority Levels : 4 priority levels per interrupt
Instruction and Data Tightly Coupled Memories : 0K ~ 1024K (configurable)
Debug : Full or reduced debug (full - 4 Breakpoint and 2 Watchpoint comparators)
DMIPS/MHz range : 0.8
CoreMarkยฎ/MHz : 1.85
MPU(Memory Protection Unit) : No
Maximum MPU Regions : 0
Trace (ETM or MTB) : No
DSP(Digital Signal Processing) : No
Floating Point Hardware : No
Systick Timer : Yes (option)
Built-in Caches : No
Tightly Coupled Memory : Yes
Bus Protocol : AHB Lite
Single Cycle Multiply : No
CMSIS Support : Yes
Dual Core Lock-Step Support : No
'ํ๋์จ์ด > ๊ณต๋ถํ๊ธฐ' ์นดํ ๊ณ ๋ฆฌ์ ๋ค๋ฅธ ๊ธ
๊ทธ๊ฒ์ ์์๋ณด์ - ARM Cortex-M4 (0) | 2020.01.29 |
---|---|
๊ทธ๊ฒ์ ์์๋ณด์ - ARM Cortex-M3 (0) | 2020.01.27 |
๊ทธ๊ฒ์ ์์๋ณด์ - ARM Cortex-M0+ (0) | 2020.01.25 |
๊ทธ๊ฒ์ ์์๋ณด์ - ARM Cortex-M0 (0) | 2020.01.23 |
๊ทธ๊ฒ์ ์์๋ณด์ - ARM Cortex Series (0) | 2020.01.21 |