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๊ทธ๊ฒƒ์„ ์•Œ์•„๋ณด์ž - ARM Cortex-M23

ARM Cortex-M23


CORTEX-M23


Cortex-M23 ํ”„๋กœ์„ธ์„œ๋Š” ARMv8-M ์•„ํ‚คํ…์ฒ˜๋กœ ๊ตฌ์„ฑ๋˜์–ด ์žˆ์œผ๋ฉฐ, baseline ๋ช…๋  ์„ธํŠธ๋ฅผ ์ง€์›ํ•˜๋Š”

์ดˆ์†Œํ˜• 2๋‹จ ํŒŒ์ดํ”„ ๋ผ์ธ ํ”„๋กœ์„ธ์„œ๋ผ๊ณ  ํ•ฉ๋‹ˆ๋‹ค.

ํŠน์ง•์œผ๋กœ ์š”์ฆ˜ ๊ฐ™์€ 4์ฐจ ์‚ฐ์—…์‹œ๋Œ€์— ๋งž๊ฒŒ IoT๋ถ„์•ผ ๋ฐ ๋‹ค์–‘ํ•œ ์ž„๋ฒ ๋””๋“œ ์‘์šฉ ํ”„๋กœ๊ทธ๋žจ์˜

๋ณด์•ˆ์— ๋Œ€ํ•œ ARM์˜ ์‹ ๊ธฐ์ˆ ์€ TrustZone์ด ํฌํ•จ๋˜์–ด ์žˆ๋Š” ํ”„๋กœ์„ธ์„œ์ž…๋‹ˆ๋‹ค.


Specifications


Architecture : ARMv8-M Baseline

Bus Interface : AMBA 5 AHB interface (Von Neumann bus architecture)

Optional single cycle I/O interface

ISA Support : Thumb/Thumb-2 subset

Pipeline : 2-stages

Software Security : Optional TrustZone for ARMv8-M with optional security

Memory Protection : Optional MPU with up to 16 regions per security state

Interrupts : Non-maskable Interrupt (NMI) and 1 to 240 physical interrupts with 4 priority levels

Interrupt Priority Levels : 8 to 256 priority levels

Wakeup Interrupt Controller : Optional for waking up the processor

from state retention power gating or when all clocks are stopped

Enhanced Instructions : Hardware single-cycle (32x32) multiply and fast (32/32) divide option

Sleep Modes :

- Integrated WFI and WFE Instructions and Sleep On Exit capability

- Sleep and Deep Sleep Signals

Debug : Optional JTAG and Serial Wire Debug ports, Up to 4 Breakpoints and 4 Watchpoints

Trace : Optional Micro Trace Buffer (MTB) or Embedded Trace Macrocell (ETM)


DMIPS/MHz range : 0.98

CoreMarkยฎ/MHz : 2.64

MPU(Memory Protection Unit) : Yes (option) (2x)

Maximum MPU Regions : 16

Trace (ETM or MTB) : ETMv3 (option) or MTB (option)

DSP(Digital Signal Processing) : No

Floating Point Hardware : No

Systick Timer : Yes (2x)

Built-in Caches : No

Tightly Coupled Memory : No

TrustZone for ARMv8-M : Yes (option)

Bus Protocol : AHB5, Fast I/O

Single Cycle Multiply : Yes

CMSIS Support : Yes

Dual Core Lock-Step Support : Yes

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