그것을 알아보자 - ARM Cortex-M7

ARM Cortex-M7

Cortex-M7 프로세서는 M4 보다 한 단계 더 뛰어난 응답성과 사용 편의성을 제공하면서

업계 최고의 고성능 프로세서로 유연한 시스템 인터페이스로 자동차, 산업 자동화, 의료 기기,

고급 오디오, 이미지 및 음성처리 그리고 센서 융합, 모터 제어를 포함하는 모든 분야에서

사용할 수 있는 엄청난 녀석입니다. 

Specifications

Architecture : ARMv7E-M

Bus Interface : 64-bit AMBA4 AXI, 32-bit AHB peripheral port, 32-bit AMBA AHB slave port

for external master (e.g. DMA controller) to access TCMs

AMBA APB interface for CoreSight debug components

ISA Support : Thumb/Thumb-2 subset

Pipeline : 6-stages superscalar + branch prediction

DSP Extension :

- Single cycle 16/32-bit MAC

- Single cycle dual 16-bit MAC

- 8/16-bit SIMD arithmetic

- Hardware Divide

Floating-Point Unit : Optional single precision floating point unit IEEE 754 compliant

(choices of none, single precision only, and single and double precision)

Instruction cache : 0 to 64 KB, 2-way associative with optional ECC

Data cache : 0 to 64 KB, 4-way associative with optional ECC

Instruction TCM : 0 to 16 MB with optional ECC interface

Data TCM : 0 to 16 MB with optional ECC interface

Memory Protection : Optional 8 or 16 region MPU with sub regions and background region

Bit Manipulation : Integrated Bit-field Processing Instructions

Interrupts : Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts

Interrupt Priority Levels : 8 to 256 priority levels

Wakeup Interrupt Controller : Optional

Sleep Modes :

- Integrated WFI and WFE Instructions and Sleep On Exit capability

- Sleep and Deep Sleep Signals

- Optional Retention Mode with Arm Power Management Kit

Debug : Optional JTAG and Serial Wire Debug ports, Up to 8 Breakpoints and 4 Watchpoints

Trace :

- Optional Instruction (ETM)

- Data Trace (DWT)

- Instrumentation Trace (ITM)

- Micro Trace Buffer (MTB)

DMIPS/MHz range : 2.14 ~ 3.23

CoreMark®/MHz : 5.01

MPU(Memory Protection Unit) : Yes (option)

Maximum MPU Regions : 16

Trace (ETM or MTB) : ETMv4 (option)

DSP(Digital Signal Processing) : Yes

Floating Point Hardware : Yes (option SP + DP)

Systick Timer : Yes

Built-in Caches : I-cache, D-cache

Tightly Coupled Memory : Yes (option 0~16MB I-TCM,D-TCM)

Bus Protocol : AXI4, AHB Lite, APB, TCM

Single Cycle Multiply : Yes

CMSIS Support : Yes

Dual Core Lock-Step Support : Yes