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๊ทธ๊ฒƒ์„ ์•Œ์•„๋ณด์ž - ARM Cortex-M0

ARM Cortex-M0


Cortex-M0


Cortex-M0๋Š” ARM ํ”„๋กœ์„ธ์„œ ์ค‘์— ๊ฐ€์žฅ ์ž‘์€ ์•„์ด๋ผ๊ณ  ํ•ฉ๋‹ˆ๋‹ค.

์ž์„ธํ•œ ์‚ฌ์–‘์— ๋Œ€ํ•˜์—ฌ ๊ถ๊ธˆํ•˜์‹œ๋ฉด ์•„๋ž˜๋ฅผ ์ญ‰์ญ‰ ๋‚ด๋ ค ๋ณด์„ธ์š”.


Specifications


Architecture : ARMv6-M

Bus Interface : AHB-Lite, Von Neumann bus architecture

ISA Support : Thumb/Thumb-2 subset

Pipeline : 3-stages

Bit Manipulation : Bit banding region can be implemented with Corstone Foundation IP

Interrupts : Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts

Wakeup Interrupt Controller : Optional

Enhanced Instructions : Hardware single-cycle (32x32) multiply option

Sleep Modes :

- Integrated WFI and WFE Instructions and Sleep On Exit capability

- Sleep and Deep Sleep Signals

- Optional Retention Mode with Arm Power Management Kit

Debug : Optional JTAG and Serial Wire Debug ports, Up to 4 Breakpoints and 2 Watchpoints


DMIPS/MHz range : 0.87 ~ 1.27

CoreMarkยฎ/MHz : 2.33

MPU(Memory Protection Unit) : No

Maximum MPU Regions : 0

Trace (ETM or MTB) : No

DSP(Digital Signal Processing) : No

Floating Point Hardware : No

Systick Timer : Yes (option)

Built-in Caches : No

Tightly Coupled Memory : No

Bus Protocol : AHB Lite

Single Cycle Multiply : Yes (option)

CMSIS Support : Yes

Dual Core Lock-Step Support : No




๋ฐ˜์‘ํ˜•

"์ด ํฌ์ŠคํŒ…์€ ์ฟ ํŒก ํŒŒํŠธ๋„ˆ์Šค ํ™œ๋™์˜ ์ผํ™˜์œผ๋กœ, ์ด์— ๋”ฐ๋ฅธ ์ผ์ •์•ก์˜ ์ˆ˜์ˆ˜๋ฃŒ๋ฅผ ์ œ๊ณต๋ฐ›์Šต๋‹ˆ๋‹ค."