ARM Cortex-M0
Cortex-M0๋ ARM ํ๋ก์ธ์ ์ค์ ๊ฐ์ฅ ์์ ์์ด๋ผ๊ณ ํฉ๋๋ค.
์์ธํ ์ฌ์์ ๋ํ์ฌ ๊ถ๊ธํ์๋ฉด ์๋๋ฅผ ์ญ์ญ ๋ด๋ ค ๋ณด์ธ์.
Specifications
Architecture : ARMv6-M
Bus Interface : AHB-Lite, Von Neumann bus architecture
ISA Support : Thumb/Thumb-2 subset
Pipeline : 3-stages
Bit Manipulation : Bit banding region can be implemented with Corstone Foundation IP
Interrupts : Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Wakeup Interrupt Controller : Optional
Enhanced Instructions : Hardware single-cycle (32x32) multiply option
Sleep Modes :
- Integrated WFI and WFE Instructions and Sleep On Exit capability
- Sleep and Deep Sleep Signals
- Optional Retention Mode with Arm Power Management Kit
Debug : Optional JTAG and Serial Wire Debug ports, Up to 4 Breakpoints and 2 Watchpoints
DMIPS/MHz range : 0.87 ~ 1.27
CoreMarkยฎ/MHz : 2.33
MPU(Memory Protection Unit) : No
Maximum MPU Regions : 0
Trace (ETM or MTB) : No
DSP(Digital Signal Processing) : No
Floating Point Hardware : No
Systick Timer : Yes (option)
Built-in Caches : No
Tightly Coupled Memory : No
Bus Protocol : AHB Lite
Single Cycle Multiply : Yes (option)
CMSIS Support : Yes
Dual Core Lock-Step Support : No
'ํ๋์จ์ด > ๊ณต๋ถํ๊ธฐ' ์นดํ ๊ณ ๋ฆฌ์ ๋ค๋ฅธ ๊ธ
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