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๊ทธ๊ฒƒ์„ ์•Œ์•„๋ณด์ž - ARM Cortex-M35P

ARM Cortex-M35P


Cortex-M35P


Cortex-M35P ํ”„๋กœ์„ธ์„œ๋Š” M33 ๋ณด๋‹ค ํ•œ ๋‹จ๊ณ„ ๋” ๋†’์€ ๋ณด์•ˆ์„ ์œ„ํ•˜์—ฌ ๋ฌผ๋ฆฌ์ ์ธ ๋ณด์•ˆ์„ ์ถ”๊ฐ€ํ•œ

ํ”„๋กœ์„ธ์„œ๊ฐ€ ๋˜๊ฒ ์Šต๋‹ˆ๋‹ค. IoT๊ธฐ๊ธฐ๋Š” ํ•ดํ‚น๋‹นํ•˜๋ฉด ์‚ฌ์ƒํ™œ ์นจํ•ด์˜ ๋ฌธ์ œ๊ฐ€ ์žˆ์œผ๋‹ˆ๊น์š”~

๊ณ„์†ํ•ด์„œ ๊ธฐ์กด ์‹œ๋ฆฌ์ฆˆ์—์„œ ์„ฑ๋Šฅ์„ ํ–ฅ์ƒ์‹œํ‚ค๋ฉฐ ์ƒˆ๋กœ์šด ๊ธฐ์ˆ ์„ ์ถ”๊ฐ€ํ•˜๋Š” ARM์ด ์ •๋ง ๋Œ€๋‹จํ•ฉ๋‹ˆ๋‹ค.


Specifications


Architecture : ARMv8-M Mainline extension

Bus Interface : 2x AMBA5 AHB interface (Harvard bus architecture)

ISA Support : Thumb/Thumb-2 subset

Pipeline : 3-stages

Software Security : Optional TrustZone for ARMv8-M, with optional Security

Physical Security : Built-in protection from invasive and non-invasive attacks

DSP Extension :

- Optional DSP/SIMD instructions

- Single cycle 16/32-bit MAC

- Single cycle dual 16-bit MAC

- 8/16-bit SIMD arithmetic

Floating-Point Unit : Optional single precision floating point unit IEEE 754 compliant

Co-processor interface : Optional dedicated co-processor bus interface

for up to 8 co-processor units for custom compute

Memory Protection : Optional MPU with up to 16 regions per security state

Interrupts : Non-maskable Interrupt (NMI) and 1 to 480 physical interrupts

Interrupt Priority Levels : 8 to 256 priority levels

Wakeup Interrupt Controller : Optional for waking up the processor

from state retention power gating or when all clocks are stopped

Sleep Modes :

- Integrated WFI and WFE Instructions and Sleep On Exit functionality

Debug : Optional JTAG and Serial Wire Debug ports, Up to 8 Breakpoints and 4 Watchpoints

Trace : Optional Instruction (ETM), Micro Trace Buffer (MTB),

Data Trace (DWT), and Instrumentation Trace (ITM)

Cache : Instruction cache


DMIPS/MHz range : 1.5

CoreMarkยฎ/MHz : 4.02

MPU(Memory Protection Unit) : Yes (option) (2x)

Maximum MPU Regions : 16

Trace (ETM or MTB) : ETMv4 (option) or MTB (option)

DSP(Digital Signal Processing) : Yes (option)

Floating Point Hardware : Yes (option SP)

Systick Timer : Yes (2x)

Built-in Caches : Yes (option 2~16kB, I-cache)

Tightly Coupled Memory : No

TrustZone for ARMv8-M : Yes (option)

Bus Protocol : AHB5, APB

Single Cycle Multiply : Yes

CMSIS Support : Yes

Dual Core Lock-Step Support : Yes


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