ARM Cortex-M23
Cortex-M23 ํ๋ก์ธ์๋ ARMv8-M ์ํคํ ์ฒ๋ก ๊ตฌ์ฑ๋์ด ์์ผ๋ฉฐ, baseline ๋ช ๋ ์ธํธ๋ฅผ ์ง์ํ๋
์ด์ํ 2๋จ ํ์ดํ ๋ผ์ธ ํ๋ก์ธ์๋ผ๊ณ ํฉ๋๋ค.
ํน์ง์ผ๋ก ์์ฆ ๊ฐ์ 4์ฐจ ์ฐ์ ์๋์ ๋ง๊ฒ IoT๋ถ์ผ ๋ฐ ๋ค์ํ ์๋ฒ ๋๋ ์์ฉ ํ๋ก๊ทธ๋จ์
๋ณด์์ ๋ํ ARM์ ์ ๊ธฐ์ ์ TrustZone์ด ํฌํจ๋์ด ์๋ ํ๋ก์ธ์์ ๋๋ค.
Specifications
Architecture : ARMv8-M Baseline
Bus Interface : AMBA 5 AHB interface (Von Neumann bus architecture)
Optional single cycle I/O interface
ISA Support : Thumb/Thumb-2 subset
Pipeline : 2-stages
Software Security : Optional TrustZone for ARMv8-M with optional security
Memory Protection : Optional MPU with up to 16 regions per security state
Interrupts : Non-maskable Interrupt (NMI) and 1 to 240 physical interrupts with 4 priority levels
Interrupt Priority Levels : 8 to 256 priority levels
Wakeup Interrupt Controller : Optional for waking up the processor
from state retention power gating or when all clocks are stopped
Enhanced Instructions : Hardware single-cycle (32x32) multiply and fast (32/32) divide option
Sleep Modes :
- Integrated WFI and WFE Instructions and Sleep On Exit capability
- Sleep and Deep Sleep Signals
Debug : Optional JTAG and Serial Wire Debug ports, Up to 4 Breakpoints and 4 Watchpoints
Trace : Optional Micro Trace Buffer (MTB) or Embedded Trace Macrocell (ETM)
DMIPS/MHz range : 0.98
CoreMarkยฎ/MHz : 2.64
MPU(Memory Protection Unit) : Yes (option) (2x)
Maximum MPU Regions : 16
Trace (ETM or MTB) : ETMv3 (option) or MTB (option)
DSP(Digital Signal Processing) : No
Floating Point Hardware : No
Systick Timer : Yes (2x)
Built-in Caches : No
Tightly Coupled Memory : No
TrustZone for ARMv8-M : Yes (option)
Bus Protocol : AHB5, Fast I/O
Single Cycle Multiply : Yes
CMSIS Support : Yes
Dual Core Lock-Step Support : Yes
'ํ๋์จ์ด > ๊ณต๋ถํ๊ธฐ' ์นดํ ๊ณ ๋ฆฌ์ ๋ค๋ฅธ ๊ธ
๊ทธ๊ฒ์ ์์๋ณด์ - ARM Cortex-M35P (0) | 2020.02.05 |
---|---|
๊ทธ๊ฒ์ ์์๋ณด์ - ARM Cortex-M33 (0) | 2020.02.03 |
๊ทธ๊ฒ์ ์์๋ณด์ - ARM Cortex-M7 (0) | 2020.01.31 |
๊ทธ๊ฒ์ ์์๋ณด์ - ARM Cortex-M4 (0) | 2020.01.29 |
๊ทธ๊ฒ์ ์์๋ณด์ - ARM Cortex-M3 (0) | 2020.01.27 |